//address的范围是：0~127(d)

module Memory(clk, reset, address, writeData, MemRead, MemWrite, readData);
    input wire[31:0] address, writeData;
    input wire MemRead, MemWrite;
    input wire clk, reset;

    output reg[0:31] readData;

    //内存按byte读取，即8bit,内存大小位128Byte
    reg[7:0] units[0:31];


    // always @(posedge reset)
    // begin
    //     readData = 32'hffffffff;
    // end

    always @(address, writeData, MemRead, MemWrite)
    begin
        if(MemRead)
        begin
            // readData[7:0] <= units[address + 0];
            // readData[15:8] <= units[address + 1];
            // readData[23:16] <= units[address + 2];
            // readData[31:24] <= units[address + 3];
            readData[0:7] <= units[address + 0];
            readData[8:15] <= units[address + 1];
            readData[16:23] <= units[address + 2];
            readData[24:31] <= units[address + 3];
        end

        if(MemWrite)
        begin
            units[address + 0] <= writeData[7:0];
            units[address + 1] <= writeData[15:8];
            units[address + 2] <= writeData[23:16]; 
            units[address + 3] <=  writeData[31:24]; 
        end
    end

endmodule